1. Field of Invention
The present invention relates to a memory. More particularly, the present invention relates to a memory structure with high coupling ratio.
2. Description of Related Art
Memory-related technology is progressing rapidly. Because of the high market demand for lighter, thinner and smaller products, flash memory is extensively used and has become a main nonvolatile memory nowadays. Because the physical size of the memory is becoming smaller and smaller, the size of each memory cell within the memory structures also must be made smaller, which results in decreasing the overlapping area of a floating gate and a control gate in each memory cell. Therefore, the coupling ratio of the floating gate and the control gate decreases. Because of low coupling ratio, the memory requires a higher voltage applied on its control gate to function. Not only the efficiency of the memory but also the reliability of the memory becomes less over a long time. Moreover, the conventional memory has a serious parasitic transistor effect that is described in detail below.
FIG. 1 to FIG. 3 show a conventional nonvolatile memory cell at different steps of the manufacturing process. In FIG. 1, a shallow trench isolation 106 in a substrate 102 can be used to define an active area 111 of a memory cell. A pad oxide 103 is located on the substrate 102. A liner oxide 104 is located around the shallow trench isolation 106. The pad oxide 103 functions as a buffer layer between a hard mask and the substrate 102. After the hard mask is removed, the surface of the shallow trench isolation 106 is apparently higher than that of the substrate 102.
Reference is made to FIG. 2. A wet etching process is performed to remove the pad oxide 103 from the substrate 102, and the upper surface of the shallow trench isolation 106 is lowered to approximate to the upper surface of the substrate 102. Then, a tunnel oxide 105 is formed at the same place where the pad oxide 103 originally is. Since the wet etching process used to remove the pad oxide 103 is isotropic, the side of the shallow trench isolation 106 is usually etched to form a concave portion 109.
In FIG. 3, a polysilicon layer is deposited on the substrate 102. Then, lithography and etching processes are performed on the polysilicon layer to form a floating gate 108. When the polysilicon layer is deposited on the substrate 102, some polysilicon material also fills in the concave portion 109 at the side of the shallow trench isolation 106. The presence of the polysilicon in the concave portion 109 causes difficulties in performing the subsequent etching process. Furthermore, there is likely an electric leakage in the region of the concave portion 109, which adversely effects the operation and reliability of the memory.